The present invention relates to a semiconductor integrated circuit which is suitable for speeding up a decoder circuit of a semiconductor memory, for example, and reducing the power consumption, and also to a semiconductor logic circuit used for the semiconductor integrated circuit.
In a semiconductor memory, which is an example of a semiconductor integrated circuit, a decoder circuit shown in FIG. 16 is heretofore used. As shown in FIG. 16, BU denotes an address buffer, PD denotes a predecoder, DD denotes a main decoder, A10 to A32 denote address input, XB1 to XB3 denote the output of a buffer (or a buffer output line), XPD1 to XPD3 denote the output of a predecoder (or a predecoder output line), W1 to W512 denote a word line, denotes an inverter, 2 denotes a static NAND logic circuit, 3 denotes a dynamic NAND logic circuit, and xcfx86 denotes a control signal. In FIG. 16, a circuit configuration including 512 word lines is shown. Reference numbers 1 to 3 denote a general inverter and NAND logic circuits respectively composed by a complimentary field effect transistor (an N-type transistor and a P-type transistor), shown in FIG. 17. It is assumed that a transistor is a metal oxide silicon field effect transistor (a MOS transistor), and it will be described below.
As shown in FIG. 16, the buffer output line XB1 is switched to a high level or a low level, according to the level of electric potential of each address input A10 to A12. A control signal xcfx86 is inputted to the NAND logic circuit 3 in the predecoder PD at a time that is a little delayed from the buffer output XB1. A phase in which the control signal xcfx86 at a low level is a precharge phase, and a phase in which it is at a high level is an evaluation phase. Therefore, when a control signal xcfx86 is switched from a low level to a high level and enters an evaluation phase, the output of the NAND logic circuit 3, to which only one buffer output signal at a high level is inputted, changes from a high level to a low level. Also, one of the predecoder output lines XPD1 is switched from a low level to a high level via the inverter and is selected.
Similarly, the buffer output line XB2 is switched to a high level or a low level, according to the level of electric potential of each address input A20 to A22. The output of the NAND logic circuit 2, to which only one buffer output signal at a high level is inputted changes to a low level, and one of the predecoder output lines XPD2 is switched to a high level via the inverter, and is selected. Similarly, one of the predecoder output lines XPD3 is switched to a high level according to the level of electric potential of each address input A30 to A32, and is selected. The output of the NAND logic circuit 3 in the main decoder, to which only one signal at a high level output from the predecoder is inputted, changes to a low level, and one of the word lines W1 to W512 is switched to a high level via the inverter, and is selected.
In a conventional type circuit, at least two columns of inverters are required to acquire the true address input and a complementary signal for a buffer output line. In FIG. 16, four columns of inverters are shown in the address buffer BU. The third and fourth columns of inverters are provided in order for a driver to acquire the true signal and a complementary signal to the buffer output line. The second column of inverter is provided for driving the inverters, and the first column of inverter is provided for shaping the input. In the meantime, as for the NAND logic circuits 2 and 3 shown in FIG. 16, the higher the number of inputs, is as shown in FIG. 17, the higher the number of the columns of N-type transistors MN1 to MNn for pulling down the output will be (on-state resistance is increased), and the speedup of circuit operation is prevented.
The object of the present invention is to provide a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is high and the true output signal and its complementary output signal having approximately the same delay time are acquired. The object is also to speed up a decoder circuit by the above semiconductor logic circuit, and to reduce the power consumption of the decoder circuit.
The speeding up of the decoder circuit, which is one of the above objects, is achieved by using a semiconductor logic circuit controlled for precharge and evaluation operation according to the polarity of a control signal input to its control terminal, and having a configuration such that the number of columns of transistors for pulling down at an output node is at most 2 or 3, even if the number of input signals (inputs) is high. The true output signal and a complementary output signal having approximately the same delay time are acquired and the electric potential of either of the above outputs is used as a reference electric potential for the above input signals for either circuit configuring the decoder circuit. The reduction of the power consumption of the decoder circuit is achieved by controlling the control terminal of the semiconductor logic circuit used for a predecoder or a main decoder by a signal output from the preceding circuit. dr
FIG. 1 is a logic diagram showing a first embodiment of a decoder circuit included in a semiconductor memory, which is an example of a semiconductor integrated circuit according to the present invention;
FIG. 2 is a logic diagram showing a second embodiment of the decoder circuit;
FIG. 3 is a logic diagram showing a third embodiment of the decoder circuit;
FIG. 4 is a logic diagram showing a fourth embodiment of the decoder circuit;
FIG. 5 is a logic diagram showing a fifth embodiment of the decoder circuit;
FIG. 6 is a logic diagram showing a sixth embodiment of the decoder circuit;
FIG. 7 is a logic diagram showing a seventh embodiment of the decoder circuit;
FIG. 8 is a logic diagram showing an eighth embodiment of the decoder circuit;
FIG. 9 is a logic diagram showing a ninth embodiment of the decoder circuit;
FIG. 10 is a logic diagram showing a tenth embodiment of the decoder circuit;
FIG. 11 is a logic diagram showing an eleventh embodiment of the decoder circuit;
FIG. 12 is a waveform chart showing the operation of the address buffer circuit shown in FIG. 11;
FIG. 13 are circuit diagrams showing an example of the logic circuit that can be used in the above embodiments;
FIG. 14 is a circuit diagram showing another example of the logic circuit which can be used in the above embodiments;
FIG. 15 is a block diagram wholly showing the semiconductor memory which is an example of the semiconductor integrated circuit according to the present invention;
FIG. 16 is a logic diagram showing an example of a conventional type decoder circuit;
FIG. 17 is a circuit diagram showing an example of the logic circuit used for the conventional type decoder circuit;
FIG. 18 is a circuit diagram showing an example of a buffer circuit which can be used in the above embodiments;
FIG. 19 is a circuit diagram showing an example in which the pulse width is reduced in the eleventh embodiment;
FIG. 20 is an explanatory drawing showing the operation of a conventional type semiconductor logic circuit;
FIG. 21 is an explanatory drawing showing the operation in a case in which pulse width is reduced in the eleventh embodiment;
FIG. 22 is a circuit diagram showing a twelfth embodiment;
FIG. 23 is an explanatory drawing showing the operation in the twelfth embodiment;
FIG. 24 show another logic circuit for input used in the twelfth embodiment;
FIG. 25 shows another activation circuit used in the twelfth embodiment;
FIG. 26 are circuit diagrams showing another load used in the twelfth embodiment;
FIG. 27 show another reset circuit used in the twelfth embodiment;
FIG. 28 is a circuit diagram showing a thirteenth embodiment;
FIG. 29 is a circuit diagram showing a fourteenth embodiment;
FIG. 30 is a circuit diagram showing a fifteenth embodiment;
FIG. 31 is a circuit diagram showing a sixteenth embodiment;
FIG. 32 is a circuit diagram showing a seventeenth embodiment;
FIG. 33 is a circuit diagram showing an eighteenth embodiment; and
FIG. 34 show a reset signal generation method.